1. Field of Invention
The present invention relates to an overlay park used in an IC fabrication process; more particularly, the present invention relates an overlay mark for checking the alignment accuracy between a lower layer defined by two exposure steps and a lithograph process for defining an upper layer, and its application in checking alignment accuracy.
2. Description of Related Art
As the line width in an IC fabrication process continues to reduce, the control of the critical dimension of a device becomes very important. When patterns of different dispositions and configurations are formed in two regions on a single wafer, it is necessary to perform two exposures to the photoresist layers of the two regions under different exposure conditions to achieve the designated critical dimension at each region. Further, two exposure steps can achieve the desired result as the pitch of the predetermined pattern is smaller than the resolution of a single exposure.
To check the alignment accuracy between the two patterns of a single wafer layer defined by two exposure steps and a subsequent wafer layer, an overlay mark is typically formed on the subsequent wafer layer according to the conventional practice as described in the process below.
As shown in FIG. 1, when a mask is used to perform a first exposure on a die region, two Y-directional bar-like exposure regions 102a are concurrently formed in a positive photoresist layer 102 above the lower the wafer layer 100 of the non-die region. Then, another mask is used for a second exposure, and two X-directional bar-like exposure regions 102b are concurrently formed in the positive photoresist layer 102. For simplicity purposes, the mask, the die region, the non-die region and the upper wafer layer are not illustrated.
The photoresist in each exposure region 102a, 102b and the exposure region in the die region are removed in the subsequent development process. Hence, in the etching process in forming the lower wafer layer pattern of the die region, two Y-directional trenches 104a and two X-directional trenches 104b are formed in a part of the lower wafer layer 100. After the completion of the upper wafer layer, a lithograph process is performed to concurrently form the photoresist pattern of the die region and two X-directional and two Y-directional bar-like photoresist figures 106, which as a portion of the overlay mark.
By measuring the distance between the median line of the two Y-directional bar-like photoresist figures 106 and the median line of the two Y-directional trenches 104a, the alignment accuracy in the X-direction between the lithograph process and the pattern defined by the first exposure step can be determined. By measuring the distance between the median line of the two X-directional bar-like photoresist figures 106 and the median line of the two X-directional trenches 104b, the alignment accuracy in the Y-direction between the lithograph process and the pattern defined by the second exposure step can be determined. However, according to such an approach, the alignment accuracy in the Y-direction between the lithograph process and the pattern defined by the first exposure step and the alignment accuracy in the X-direction between the lithograph process and the pattern defined by the second exposure step can not be determined. Hence, this type of overlay marks on determining alignment is not completely effective.
Moreover, if the abovementioned four trenches are all defined in the first (or the second) exposure step, the alignment accuracy in the X-direction and in the Y-direction between the lithograph process and the patterns defined by the first (or the second) exposure step can be estimated. However, it is unable to estimate the alignment accuracy of between the lithograph process and the patterns defined by the second (or the first) exposure process. In order to be able to estimate the alignment accuracy in the X-direction and the Y-direction between the patterns defined in the first and the second exposure process respectively with the lithography process, the above-mentioned four trenches are defined in the first exposure step and another four trenches are defined in another part of the low wafer layer during the second exposure step. However, such an arrangement increases the area occupied by the overlay mark by two times.
Additionally, regardless of which type of the overlay mark, it is unable to estimate the alignment accuracy in the X-direction and in the Y-direction between the low wafer pattern defined in the first exposure and the low wafer pattern defined in the second exposure.